SystemVerilog Constraint Help for Negative/Postiive numbers

SystemVerilog
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1

Hi,

I have three values which are signed logic vectors as shown below. I am trying to build a constraint where the sum of the three numbers, positive and negative included should be less than a constant.

parameter signed LIMIT = 200;
rand logic signed [15:0] a;
rand logic signed [15:0] b;
rand logic signed [15:0] c;

constraint limit {a+b+c < LIMIT);

I tried the above code snippet but it does not obey the constraint.I would like the value of a ,b and c be negative/and or positive but the sum to be less than the constant.

How can i write this constraint ?

2

In reply to kk9110:

I am not certain how the parameter is interpreted internally
( As Signed OR Unsigned ?? .
I believe LRM isn’t clear about this so the result might vary across Simulators !! )

Verilog Basics dictate ::
If it’s signed the each Operand in the expression would be treated as Signed ,
else Each Operand would be treated as Unsigned !!

It would be easier to analyze if you had posted the results too

3

In reply to ABD_91:

parameter is being treated as signed. I had actually defined it as follows. (Typo in my original post)

parameter signed LIMIT = 200;

I do see that the values for a,b and c are getting randomized between negative and positive numbers. But its just that the sum of the three numbers seems to violate the value of LIMIT.

4

In reply to kk9110:

I believe there could be a misinterpretation on your part .
Realize if the MSb of a , b , c are 1’b1 , they indicate Negative Numbers !!

One could read it as unsigned ( which isn’t true )

What’s the sum you Observe ? Also How are you displaying / Calculating the sum ?

5

In reply to ABD_91:

Assume the following

LIMIT - 3H
A - 020B (Hex), B - FD9C (Hex) and C - 0A44 (Hex)

Sum -09EB (Hex) > LIMIT (3 Hex)

I am seeing the values as all “Hex” so if I do see a MSB of ‘1’ i know the number is negative.

6

In reply to kk9110:

Besides the ‘signed’ keyword I believe you have changed the Packed Dimensions too in Original Code !!

[ Previously it was [7:0] for all 3 Variables . ]

Anyways with [15:0] there are Chances of Overflow too .

(1) Also LIMIT is 200 which is 32-bit Signed .
(200) in Decimal is (C8) in hexadecimal .

Why are you expecting it to be 3H ??

(2) Try to display all 3 Variables in “%0d” Format String

7

In reply to ABD_91:

Sorry should have been clear. The LIMIT is a parameter and I had it parameterized to 3 hex. I made the following changes and it seems to work well now.

parameter signed LIMIT = 200;
rand logic signed [15:0] a;
rand logic signed [15:0] b;
rand logic signed [15:0] c;

rand logic signed [17:0] sum;

constraint c_sum {sum < LIMIT;}
constraint limit {a+b+c < sum;