Systemverilog constraint on a enum type

SystemVerilog
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1

Hello, My code below is giving me the following errors. I am unable to figure out the mistake in this approach.

assert(cl_ob.randomize());
|
ncsim: *W,SVRNDF (./testbench.sv,26|25): The randomize method call failed.
Observed simulation time : 0 FS + 0
ncsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints:
if(i != j) fruits[i] != fruits [j] ;} (./testbench.sv,11)
constraint num_fruits_c1 { foreach(num_fruits[i]) (./testbench.sv,14)
ncsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints:
rand variables:
fruits[4] [./testbench.sv, 6] <apple=0, orange, banana, strawberry, pineapple>
num_fruits[4] [./testbench.sv, 7]
ncsim: *E,ASRTST (./testbench.sv,26): (time 0 FS) Assertion unique_array.__assert_1 has failed
apple : 0 : 0
apple : 0 : 0
apple : 0 : 0
apple : 0 : 0
ncsim: *W,RNQUIE: Simulation is complete.


typedef enum int { apple, orange, banana, strawberry, pineapple } fruit_e;
int fruit_num_array [fruit_e] = '{apple : 10, orange : 20, banana : 30, strawberry : 40, pineapple : 50} ;
 
module unique_array;
  class data_cl;
    rand fruit_e fruits[4];
    rand int num_fruits[4];
    rand int subset[4];
    constraint unique_fruits_c { foreach(fruits[i]) 
      		  		   foreach(fruits[j])
                                      if(i != j) fruits[i] != fruits [j] ;} 
    constraint num_fruits_c { foreach(num_fruits[i]) 
      				num_fruits[i] inside {fruit_num_array} ;} 
    constraint num_fruits_c1 { foreach(num_fruits[i])
      				foreach(fruits[j]) 
                                       if(i==j) num_fruits[i] == fruit_num_array[fruits[j]]; }
    constraint subset_c {foreach(subset[i]) subset[i] inside {[0.15 * num_fruits[i] : 0.75 * num_fruits[i]]}; }
 
  endclass
 
  data_cl cl_ob;
 
  initial
  begin
     cl_ob = new();
    assert(cl_ob.randomize());
    foreach(cl_ob.fruits[i])
      $display("%s : %0d : %0d",cl_ob.fruits[i].name(), cl_ob.num_fruits[i], cl_ob.subset[i]);
  end
endmodule
2

In reply to aksistla:

The constraint on subset is assigning non integral values to integral property.

constraint subset_c {foreach(subset*) subset[i] inside {[0.15 * num_fruits[i] : 0.75 * num_fruits[i]]}; }

Lets say for example num_fruits[i]=10. Then value of subset[i] is to be inside 1.5 to 7.5. This is not acceptable.

According to SystemVerilog LRM 1800-2012 , Section 18.5.3, the constraint solver can solve integral type constraints:

The solver can randomize singular variables of any integral type.
Constraints can be any SystemVerilog expression with variables and constants of integral type (e.g.,
bit, reg, logic, integer, enum, packed struct).
Constraints support integer value sets and the set membership operator

You can use [i]post_randomize* function to set the values in subset variable. After removing the subset constraint, I am seeing proper randomization happening using VCS.

//Output: (subset is signed)
banana : 10 : 1193078623
strawberry : 10 : -1364192802
pineapple : 10 : -505257340
apple : 10 : 2045249375
3

In reply to sharvil111:

You can also convert the expression to integral by writing

constraint subset_c {foreach(subset) subset[I] inside {[15 * num_fruits[I]/100 : 75 * num_fruits[I]/100]}; }

But another problem is you are not allowed to use a random variable as an array select

fruit_num_array[fruits[j]]

cannot be used. You’ll need to nest another foreach (fruit_num_array[k])

4

In reply to dave_59:

But another problem is you are not allowed to use a random variable as an array select
fruit_num_array[fruits[j]]
cannot be used. You’ll need to nest another foreach (fruit_num_array[k])

Agree. This got out of my sight. Yet “fruit_num_array[fruits[j]];” works in VCS.