SystemVerilog Constraint

SystemVerilog
1

How to write SystemVerilog constraint for random integer variable such that it is Even number for 70% of times, and Odd number for 30% of times ?

2

In reply to vihar pansara:

Try this (I limited the integer range from 0-30):

module top;

class TFoo;
   rand int myint;

   constraint random_number_c {
      myint inside {[0:30]};
   }
   constraint even_odd_c {
	myint % 2 dist { 0:=7, 1:=3};
   }
endclass

TFoo f = new;
int status;

initial
begin
	for(int i = 0; i < 20; i++)
	begin
		status = f.randomize();
		$display("%0d: myint = %0d", i, f.myint);
		$display(" ");
	end
end

endmodule
1 Like
3

Thanks @graeme_jessiman.