SystemVerilog Concurrent Assertion Non Constant Delay Range

SystemVerilog
,
1

How to write the following property without Non Constant expression error?

property rising_check;
@(posedge clk) disable iff(~reset) $rose(a) |-> ##[0:cycle] ($rose(b));
endproperty

2

Hi,

passing an argument is property will not work ? like below

property rising_check(cycle);
@(posedge clk) disable iff(~reset) $rose(a) |-> ##[0:cycle] ($rose(b));
endproperty

assert rising_check(delay);

3

In reply to cool_cake20:

Yes. At compile time the delay expression must be constant. I am not able to find a way to pass an argument as the max number of clock cycle delay.

4

I think so u can try this

property rising_check;
int cycle_delay;
@(posedge clk) disable iff(~reset) (rose(a),cycle_delay = cycle) |-> (cycle_delay>0,cycle_delay=cycle_delay-1)[*0:] ##0 cycle_delay==0 ##0 ($rose(b));
endproperty

Please correct me if i am wrong.

5

Hi
If it is not achievable with assertion why don’t try in other way like below.



  @(posdedge a);
   fork
    begin
   @(posdedge b); // waiting for posedge of b
    end
   begin
    forever
     begin
     @posedge clk; 
     clk_cnt++
     end
    end
   join_any
   disable fork;
   if(~(clk_cnt inside[0:cycle]))
   $error
 clk_cnt=0;