Assertions can be subdivided into immediate and concurrent assertions.my doubt is System Verilog doesn’t allow the usage of concurrent assertions. Concurrent assertions are illegal within classes? A concurrent assertion statement may be specified in any of the following:
An always procedure or initial procedure as a statement, wherever these procedures may appear
A module
An interface
A program
A generate block
A checker
than what about immediate assertions? Where can implemented in it?
In reply to anvesh dangeti:
Immediate assertion are allowed in classes within functions and tasks.
Concurrent assertions are not allowed. My papers (links below) provide guidelines on how to handle concurrent assertions in classes or in modules, as there are special cases where you want to do that.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
- Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com - Papers:
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy - Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy