Is it possible to send parameters to SystemVerilog Assertion Property (like sending parameters to tasks)?
Actually I have many signals, which should have the same property (behavior). Should I write a seperate property for each signal (they are about 100…)?
What’s the best solution for my case?
Can I use a generate statement for the properties?
property_declaration ::=
property property_identifier [ ( [ property_port_list ] ) ] ;
{ assertion_variable_declaration }
property_statement_spec
endproperty [ : property_identifier ]
property_port_list ::=
property_port_item {, property_port_item}
property_port_item ::=
{ attribute_instance } [ local [input] ] property_formal_type
formal_port_identifier {variable_dimension}
[ = property_actual_arg ]
... See 1800 for more. An example of a property declaration
property P2
(ack, // argument , implicit untype
sequence seq1,
event evnt, // event identifier
property P1,
local int lv_data=0, // local variable
logic w // argument
);
@(evnt) (ack, lv_data=data1) ##1 seq1 |=>
w && lv_data==mem_data |=> P1;
endproperty : P2
You can use a generate statement for the properties if it makes sense, For example, from my SVA Handbook 4th Edition
generate for (genvar i=0; i<=15; i++)
begin
property p_arbiter;
bit[16:0] v;
(req*==1'b1, v=0, v[i+1]=1'b1) ##0 req < v |->
grnt[i]==1'b1 ##0 $onehot(grnt);
endproperty : p_arbiter
ap_arbiter: assert property(@(posedge clk) p_arbiter);
end
endgenerate
Is it possible to send parameters to SystemVerilog Assertion Property (like sending parameters to tasks)?
From your use of [i]parameters* instead of arguments I get the feeling that you are coming from a VHDL world. Key points here:
A SystemVerilog “argument” is a VHDL “parameter”
A SystemVerilog “parameter” is a VHDL “generic”
Please, Please … when speaking SystemVerilog, DON’T use “parameter” when you mean “argument” … It confuses your audience
IEEE STANDARD VHDL LANGUAGE REFERENCE MANUAL Std 1076-2008 “Certain functions, designated pure functions, return the same value each time they are called with the same values as actual parameters.
IEEE STANDARD FOR SYSTEMVERILOG
The system functions that may be used in constant system function calls are pure functions, i.e., those whose value depends only on their input arguments and which have no side effects.