SystemVerilog Assertion label

SystemVerilog
,
1

I"m new to using assertions and I was going through some best practices paper from a website. The below assertion compiles fine.

  always @* begin
    ERR_reset_went_unknown: assert(!$isunknown(Reset))
    else begin
      $error("ERR_reset_went_unknown");
      repeat(2) @(posedge Clock);
      $finish;
    end
  end

However, if I remove the else portion, I get a compile error.

  always @* begin //The always @* trigger will also catch the 0-to-X/Z-to-1 transitions
    ERR_reset_went_unknown: assert(!$isunknown(Reset))
    assert(!$isunknown(Reset));
  end

** Error: counter_asserts.sv(27): ‘ERR_reset_went_unknown’ already exists; must not be redefined as a named block

If I remove the label, ERR_reset_went_unknown:, above it compiles.
Why is this?

Thanks,
Mark

2

In reply to markylew:
All assertions labels must be unique.
Also, watch the syntax and the use of the end of statement “:”.


module m; 
   bit Reset, clock; 
   always @* begin
    ERR_reset_went_unknown: assert(!$isunknown(Reset))
    else  $error("ERR_reset_went_unknown");  
   end
  
  always @* begin
    ERR_reset_went_unknown2: assert(!$isunknown(Reset));
    // else  $error("ERR_reset_went_unknown");  
   end
  
  always @* begin //The always @* trigger will also catch the 0-to-X/Z-to-1 transitions
    ERR_reset_went_unknown3: assert(!$isunknown(Reset));
    
    assert(!$isunknown(Reset));
  end
  
  initial begin 
      repeat(2) @(posedge clock);
      $finish;
  end
  
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to ben@SystemVerilog.us:

Thanks Ben!

4

In reply to markylew:

Hi Ben,
Can you elaborate on “the use of the end of statement “:””?

Also, why isn’t there a semicolon “;” after the below assert statement?

always @* begin
    ERR_reset_went_unknown: assert(!$isunknown(Reset))
    else  $error("ERR_reset_went_unknown");  
   end

Thanks,
Mark

5

In reply to markylew:
You have to look at the syntax.
1800’2018 16.3 Immediate assertions


immediate_assertion_statement ::=
   simple_immediate_assertion_statement
 | deferred_immediate_assertion_statement
...
simple_immediate_assert_statement ::=
  assert ( expression ) action_block

action_block ::=
statement_or_null
| [ statement ] else statement_or_null

 ERR_reset_went_unknown: assert(!$isunknown(Reset))  // assert ( expression )
    else  $error("ERR_reset_went_unknown");  // [ statement ] else statement_or_null
// note that from the syntax on the action_block the [statement] is optional. 
// thus, thus the following is in ERROR
assert(!$isunknown(Reset)); else  $error("ERR_reset_went_unknown"); 
// because 
assert(!$isunknown(Reset));  // this follows the syntax of 
assert ( expression ) null; // The ";" is the end of simple_immediate_assert_statement 
// so what you have 
assert(!$isunknown(Reset));  // a legal statement, DONE here with that statement 
else  $error("ERR_reset_went_unknown"); // else?  no legal statement starts with "else' 
// what is that funny "else' statement? It's hanging there!! illegal!

Ben SystemVerilog.us

6

In reply to ben@SystemVerilog.us:

Thank you for clarifying that! :)