Systemverilog assertion

Can we use $signed in SVA to check for a range of values between [-31,+31]? Or we have to convert the range to unsigned value to check the defined range in SVA irrespective of the variable declared to store the value being declared as signed or unsigned?

In reply to Nimisha Varadkar:

SVA only requires that you use expressions that return non-zero for true, or zero for false.

You need to have a basic understanding of how Verilog expressions work regardless of whether they are used in an assertion, random constraint, or anywhere else. You might want to look at my webinar which explains how expressions get evaluated from random constraints, but it applies equally well to assertions.