For a system verilog testbench, how to supress a specific ERROR info in log

SystemVerilog
1

Hi guys,

I have a legacy testbench using system verilog, and there is a requirment to supress some error info when simulate.
Does anyone know the common practice to do that?

2

In reply to philerpeng:

Hi guys,
I have a legacy testbench using system verilog, and there is a requirment to supress some error info when simulate.
Does anyone know the common practice to do that?

How are you displaying the error messages?

3

In reply to philerpeng:

If by “legacy testbench” you mean something that was not UVM based, you can still convert the messages to use the UVM reporting API by changing the $display(“message”) to `uvm_error(“uniqueid”,“message”). Then you can control the messages from the command line with +uvm_set_action from the command line, or within your code.

4

In reply to dave_59:

Thanks for sugesstions.

I am a SV and UVM practicer, not familiar with OVM.
Let me give a description of test env and my requirement.

The tesbench is a pure system verilog tb, but it has a register model(somewhat like UVM register model), the model is writen like:

typedef struct packed{
bit      cmd_reg_read_0;
bit[8:0] cmd_reg_9_1;
bit      cmd_reg_cmd_read_status_10;
...
bit[1:0] cmd_reg_31_30;
} reg_cmd_reg_t;

class reg_cmd_reg extends ovm_register #(reg_cmd_reg_t);
  function new(string name, ovm_named_object p);
      super.new(name,p);
      WMASK='h20001401;
      RMASK='hFFFFFFFF;
      W1CLRMASK='h0;
      W0SETMASK ='h0;
      CLRONREAD='h0;
      SETONREADMASK='h0;
   endfunction
endclass

class dev_reg_file extends ovm_register_file;
   reg_cmd_reg r_cmd_reg;
   ...
   ...
  
   function new(string name, ovm_named_object p);
      super.new(name, p);
      r_cmd_reg = new("cmd_reg",this);
      add_register(r_cmd_reg.get_fullname(),'h010,r_cmd_reg);
   endfunction
endclass

there is a task like reg_wr(addr,data) is used to configure register.

my questions are:

  1. i checked some doc of OVM, does OVM have register model like UVM?
  2. in some testcase, i used reg_rd(ADDR0, rdata) operation on purpose, and ADDR0 is not a
    valid(not mapped in model) addr.
    Simulator complains with OVM_ERROR, this ERROR is not caused by $display.
    So any idea to supress this OVM_ERROR?
5

In reply to philerpeng:

the ERROR just like:
OVM_ERROR @1474731 ns: reporter [ovm_register_container] lookup register by address(): Offset/Address 0xffc has not been mapped.

6

In reply to philerpeng:

The OVM did not have a register model. There were a number of proposals, and the one you show did not make it into the UVM standard. Even though all the class names are prefixed with ovm_*, they are imported as a separate package.

The OVM reporting system was migrated to the UVM, so you can use the same ovm_top.set_id_action() method to suppress the error. But are you looking to fix the error rather than suppress it?

7

In reply to dave_59:

Thanks all, it’s helpful for me.