Will two if blocks inside an always block be executed sequentially or parallel?
I am aware that all the statements within always are executed sequentially but what about the if blocks ?
always @(posedge clk) begin
if () begin
.....
count = coun+1;
end
if () begin
....
count = count + 1;
end
end
Will the first if execute first “always” ?
Thanks in advance for the help!
In reply to Bhaskar44:
The answer is YES. However, good coding practice would be more something like:
always @(posedge clk) begin
static int x; // stays on in value throughout simulation
automatic int y; // in life at every entry till end of always statement
if () begin
.....
count <= coun+1; // nonblocking assignment
x= ..;
y= ..;
end
if () begin
....
count <= count + x +y;
end
end
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
Hi Ben!
I got the clarification for my doubt, however I was wondering how using the static and automatic variables makes my code better and reliable:
For ex: I said there is a clock, but say I am monitoring events, and there are 20 events, which occur regularly, so my code would be more like this:
always @(event_t1) begin
if () begin
.....
if (a<8)
if (a<4)
....
else if (a<7)
....
if (a==6)
....
count = count+1;
end//if
end // always
And this is a behavioral code, no need for synthesis.
Currently I have this working (for most cases), but however I am afraid that my model would break because of race condition for “count”, because everytime I enter an if condition, i use the count to do something, increment, and then use the incremented count to do something - all these for each event sense!
Is there a better coding approach than the above, hence wass interested in knowing how using static and automatic would make a difference ?
Also, I have always followed a practice of no blocking assignments within a clocked block. But the above solution you have provided has a mix of both NBA and blocking. Could you also please clarify on this ?
Thanks in advance!
In reply to Bhaskar44:
I suggest that you study, through 1800 or books or sites, the definition and uses of static,
automatic variables and tasks.
In an always block, locally defined static variables exists all the time, just like variables defined in modules. Locally defined automatic variables exist throughout the lifetime of the block. Locally defined variable can only be assigned as blocking. Typically, automatic variables are used as temps in the computational process since they are disposed of at the end of the block (or task). Locally static variables are used as storage.
Since you addressed the topic of race condition, study the SystemVerilog time slot regions (see 1800’2012 4.4.3 PLI regions
So the question is really all about applications.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to Bhaskar44:
Let me go back to answer your original question. All statements you put inside a begin/end block execute sequentially, meaning the next statement does not execute until the previous statement finishes its execution. An assignment is a statement. An if is a conditional branching statement. A begin/end block is a single compound statement. You can use a begin/end statement anywhere a single statement is allowed, and the statement(s) inside the block execute sequentially as well. The execution of the begin/end block statement does not complete until it has finishes the last statement in its sequence.
There are no races between statements within a begin/end block because only one statement is executing at any one time. However, a fork/join block is also a single compound statement, but the statements inside a fork execute in parallel. So you can have races between statements in a fork/join, and you can also have races between multiple initial and always blocks if they execute simultaniously.
In reply to dave_59:
Thanks Dave for a detailed response and explaining it in simple terms. My apprehensions are cleared now!