System Verilog Polymorphism

SystemVerilog
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1

Hello,

Suppose we have a class:register and another class rege that extends registers(subclass of register).

if we declare a handle for both the classes :

register c1;

rege c2=new;

c1=c2;

rege c3;

$cast(c3,c1);

i am not able to understand why cant we simply do c3=c2 and access the elements of reg class? Why do we need to use the cast operator? Basically i am not able to understand the importance of polymorphsm in this regard?

2

In reply to universe:

Downcasting without using a dynamic $cast is never allowed. $cast must check the validity of the handle stored in c1 before it can make the assignment. See Why downcasting is not allowed in SystemVerilog? | Verification Academy