System Verilog Interface used in multiple places

We have an interface which needs to be used in 2 places in our Testbench.
I am planning to use single interface and write multiple instances of them.

But we have an need to check for assertions in only 1 of them.

interface intf1();
.
.
.
`include “assertions.sv”

endinterface

interface intf2();
.
.
.
endinterface

Except the assertions include everything else is same. how can we use multiple instances of a single interface in this scenario

In reply to Jack Bryan:

I would put the assertions in a separate module and use the bind construct as required.