System Verilog Force Procedural Statement

SystemVerilog
1

Hi All,

In SystemVerilog LRM [1800-2012] Section: 10.6.2, it is mentioned the following:

“A force or release statement shall not be applied to a variable that is being assigned by a mixture of continuous and procedural assignments”

Could i get an example of this mixture assignment ?

Thanks,

2

In reply to aehsan:

module top;
  logic  v[2];
  assign v[1] = 1;
  initial begin
    v[0] = 0;
  end
endmodule