In reply to Design Engineer:
As you are new to SystemVerilog, you should try working on many small programs related to every topic like datatypes, OOP, mailbox, interface, threads, etc, and get expertise. Then you can start developing the TB for small designs like counter, FIFO, etc using the concepts you have learned. This way you can improve your programming skills.
You can download SystemVerilog LRM which is freely available to learn SystemVerilog & there are many online courses available to learn SystemVerilog, such as the Verification Academy.