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SystemVerilog
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  • System verilog FIFO

System verilog FIFO

SystemVerilog 6890
#queues #systemverilog 23 FIFO ordered Queue 2
Design Engineer
Design Engineer
Forum Access
24 posts
May 18, 2020 at 3:39 am

How to verify the functionality of FIFo using Queue methods?

Replies

Log In to Reply
sbellock
sbellock
Full Access
192 posts
May 18, 2020 at 8:31 am

In reply to Design Engineer:

Populate your input queue and save a copy of it. Feed the contents of that queue into the FIFO and capture the output of the FIFO into another queue. Compare the output queue with the original queue. If they match your FIFO functionally works.

shanthi
shanthi
Full Access
89 posts
May 18, 2020 at 9:56 am

In reply to sbellock:

During a write to FIFO, push the data into the queue and during a read from FIFO pop the data from the queue and compare the dataout of FIFO with the data popped from the queue. Remember that push & pop should be in opposite direction. While pushing & popping the data from the queue you can compare the size of the queue to set empty & full flags.A small snippet of code is shown below for your reference(Considering FIFO of 8 bits wide & 16 bytes depth)

bit[7:0]fifo_model[$];
bit [7:0]ref_data;
bit full;
bit empty;
if(xtn.rst)
  begin
   fifo_model.delete();
   full = 0;
   empty = 1;
  end
 
if(xtn.wr)
  begin
    if(fifo_model.size==16)
      full = 1; 
    else
     fifo_model.push_back(xtn.data_in);
  end
 
if(xtn.rd)
  begin
    if(fifo_model.size == 0)
       empty =1;
    else
      begin
        ref_data = fifo_model.pop_front();
        if(xtn.data_out == ref_data)
          $display("DATA COMPARED SUCESSFULLY");
       else
          $display("DATA COMPARISION FAILED");
     end
   end
 
 

You can add the logic to compare the full & empty conditions as well

Regards,
Shanthi V A
www.maven-silicon.com/blog

Design Engineer
Design Engineer
Forum Access
24 posts
May 18, 2020 at 10:35 am

In reply to sbellock:

Thanks @ Sbellock

As I am new to System verilog,I struck in coding. But i have gone through all the concepts in it.Can you suggest me what I can do to improve my programming skills?

Design Engineer
Design Engineer
Forum Access
24 posts
May 18, 2020 at 10:36 am

In reply to shanthi:

Thats the nice idea@Shanthi
Thanks for it
I will try with this

Can you suggest me some tips to improve my programming skills in System verilog?

shanthi
shanthi
Full Access
89 posts
May 26, 2020 at 3:16 am

In reply to Design Engineer:

As you are new to SystemVerilog, you should try working on many small programs related to every topic like datatypes, OOP, mailbox, interface, threads, etc, and get expertise. Then you can start developing the TB for small designs like counter, FIFO, etc using the concepts you have learned. This way you can improve your programming skills.

You can download SystemVerilog LRM which is freely available to learn SystemVerilog & there are many online courses available to learn SystemVerilog, such as the Verification Academy.

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