System verilog event queue

SystemVerilog
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1

In SystemVerilog there are two kinds of assertions: immediate and concurrent assertions .In which systemverilog event queue region assertions are triggered?

2

In reply to anvesh dangeti:

“The values of variables used in assertions are sampled in the Preponed region of a time slot, and the assertions are evaluated during the Observed region. …”

http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf

3

In reply to yourcheers:

And to add to this, an immediate assertion gets executed in whatever region the procedural block that contains it is executing. There is no sampling of variable values.

4

In reply to anvesh dangeti:

There is one more type of immediate assertions called Deferred Immediate Assertions which will be executed in postponed region. These deferred immediate assertions will work on the settled values of the variables in a single time step.

Putta Satish

5

In reply to puttasatish:

Thanks for the reminder about deferred immediate assertions. Their expressions also get executed in whatever region the procedural block that contains it is executing. However, their reporting gets deferred until the postponed region to allow for repeated execution to flush out glitches.