System verilog-Design

How to assign 4 pattern of data for a continous 4 clock cycle?

In reply to Design Engineer:

If I understand you correctly, you have a 4-data pattern (e. G., 10,14,45,78> that you want to continuously cycle in that order.

  1. I would store the pattern into a memory.
  2. concatenate the msb address bits with 2 bits of a counter
  3. Fetch the memory from that concatenated address and increment the counter.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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