I've the following system verilog package in my testbench;
`define WIDTH 'h64
When this package get's imported into my agent package and tried to use the define in my driver class like below;
class driver extends uvm_driver#(transaction);
task run_phase(uvm_phase phase);
length = `WIDTH;
The questa tool is returned with compile error that as below;** Error: ** while parsing file included at ../../../../test/agents/phy_agent/phy_agent_pkg.sv(16)
** at ../../../../test/agents/phy_agent//src/phy_driver.sv(213): (vlog-2163) Macro `WIDTH is undefined
I don't see any problem while running with other tools...
Can anybody suggest on how to make it work in questa?
I'm using 10.3a_1 version...