System Verilog: `define error while running with questa tool

SystemVerilog
, ,
1

Hi Friends,

I’ve the following system verilog package in my testbench;

package common_pkg;
      
    ..... 
    `define WIDTH 'h64 
   endpackage

When this package get’s imported into my agent package and tried to use the define in my driver class like below;

class driver extends uvm_driver#(transaction);
    .......    
    .......
    task run_phase(uvm_phase phase);
     forever begin
      ........
      length = `WIDTH;
     end  
    endtask 
   endclass

The questa tool is returned with compile error that as below;
**** Error: ** while parsing file included at …/…/…/…/test/agents/phy_agent/phy_agent_pkg.sv(16)
** at …/…/…/…/test/agents/phy_agent//src/phy_driver.sv(213): (vlog-2163) Macro `WIDTH is undefined**
I don’t see any problem while running with other tools…
Can anybody suggest on how to make it work in questa?
I’m using 10.3a_1 version…
Thanks,
Regards,
Mahesh.

2

In reply to mahesh_424:

Change your
`define into a
parameter. Text macros get compiled and used before parsing any SystemVerilog code, so they cannot be part of a package and later imported.

The reason it appears to work in one tool and not another is because of the way the tool treats files in compilation units.

See this reply and related links.

3

In reply to dave_59:

Hi Dave,
Thank you very much for your reply. I’ve changed to parameter and things are working fine.

Regards,
Mahesh.