System verilog constraints on Base class

In the following code, we have 2 constraints on same variable, declared in both base class and derived class. The constraint name is also the same.
When we print the value of the variable after performing randomization, the randomization of derived class variable behaves on the expected lines, constraint c_x was applied and the result was 'd2. But for the base class variable , even though randomization is successful, the constraint is not applied!!!
Comments?

class base;
  rand bit [4:0] c;
  constraint c_x { c == 'd1; }
  function void display();
    this.randomize();
    $display("Base    c:%0d",c);
  endfunction
endclass

class derived extends base;
  rand bit [4:0] c;
  constraint c_x { c == 'd2; }
  function void display();
    this.randomize();
    $display("Derived c:%0d",c);
    super.display();
  endfunction
endclass

module top;
  derived b;
  
  initial begin
    b = new;
    repeat(2)
    b.display();
  end
endmodule

Simulation result :
CPU time: .243 seconds to compile + .330 seconds to elab + .280 seconds to link
Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version Q-2020.03-SP1-1; Runtime version Q-2020.03-SP1-1; Apr 22 00:47 2021
Derived c:2
Base c:27
Derived c:2
Base c:7
V C S S i m u l a t i o n R e p o r t

In reply to pavan_hyd:

See this just asked yesterday: how the constraint is executed | Verification Academy