System verilog constraints

Hi,

I have a constraint defined as follows :
rand bit a, b, c, d

constraint name_constraint {


soft a inside {1'b0, 1'b1}
soft b inside {1'b0, 1'b1}
soft c inside {1'b0, 1'b1}
soft d inside {1'b0, 1'b1}


}

The only valid constraints are:

  1. a=1, d=1 , b=0, c=0
  2. a=0, b=1, c=1, d=0

How do i solve and constraint so that i get above behavior

Thanks

In reply to tejasakulu:

My apologies if i haven’t understood your questions correctly.

constraint name_constraint {
  {a,b,c,d} inside { 4'b1001,4'b0110};
}

As a,b,c,d are single bits, the soft constraints you mentioned are implied and obvious :)

Hey Tejas

Hope you are expecting following output,Where ‘d’ is always 1 via CRV and in second case its toggled for each variables.



//code - 1
class constarint_abcd;
  
rand bit a;
rand bit b;
rand bit c;
rand bit d; 
  
  constraint a_b_c_d { {d} inside { 1 } ;}
     
endclass


// Code -2 
class constarint_abcd;
  
rand bit a;
rand bit b;
rand bit c;
rand bit d; 
  
  constraint a_ { {a} inside {$onehot(a)} ;}
  constraint b_ { {b} inside {$onehot(b)} ;}
  constraint c_ { {c} inside {$onehot(c)} ;}
  constraint d_ { {d} inside {$onehot(d)} ;}
    
  
endclass



//solution space 1
    
Compiler version Q-2020.03-SP1-1; Runtime version Q-2020.03-SP1-1;  Oct 19 05:09 2021
a:1   b:1 c:1 d=1
a:0   b:1 c:0 d=1
a:1   b:0 c:1 d=1
a:1   b:1 c:1 d=1
a:1   b:1 c:0 d=1
           V C S   S i m u l a t i o n   R e p o r t 
Time: 0 ns
CPU Time:      0.360 seconds;       Data structure size:   0.0Mb  

// solution space - 2

../simv up to date
CPU time: .206 seconds to compile + .238 seconds to elab + .289 seconds to link
Chronologic VCS simulator copyright 1991-2020
Contains Synopsys proprietary information.
Compiler version Q-2020.03-SP1-1; Runtime version Q-2020.03-SP1-1;  Oct 19 05:19 2021
a:1   b:1 c:0 d=0
a:0   b:0 c:1 d=1
a:0   b:1 c:1 d=1
a:0   b:0 c:0 d=0
a:1   b:0 c:1 d=0
           V C S   S i m u l a t i o n   R e p o r t 



//code -3 
class constarint_abcd;
  
rand bit a;
rand bit b;
rand bit c;
rand bit d; 
  
  constraint a_  { a inside { ~b} ;}
  constraint b_  { b inside { ~c} ;}
  constraint c_  { c inside { ~d} ;}
  constraint d_  { d inside { ~a} ;}
  
endclass

// solution space -3 

a:1   b:0  c:1  d=0
a:1   b:0  c:1  d=0
a:0   b:1  c:0  d=1
a:0   b:1  c:0  d=1
a:0   b:1  c:0  d=1
a:1   b:0  c:1  d=0
a:0   b:1  c:0  d=1
a:1   b:0  c:1  d=0
a:1   b:0  c:1  d=0