Passing blk argument from terminal
vsim +blk=ch0_ddr
`define csr_pkg(blk)\
`define CSR_``blk`` \
`ifdef CSR_ch0_ddr\
import csr pkg blk csr::*;\
csr_block_``blk`` reg model gen;\
`elsif CSR_ch1_ddr\
import csr pkg blk csr::*;\
csr_block_``blk`` reg model gen;\
`elsif CSR_ch2_ddr\
import csr pkg blk csr::*;\
csr_block_``blk`` reg model gen;\
`elsif CSR_ch3_ddr\
import csr pkg blk csr::*;\
csr_block_``blk`` reg model gen;\
`elsif CSR_ch4_ddr\
import csr pkg blk csr::*;\
csr_block_``blk`` reg model gen;\
`elsif CSR_ch5_ddr\
import csr pkg blk csr::*;\
csr_block_``blk`` reg model gen;\
else \
import csr pkg_blk csr::* \
csr_block_``blk``_csr reg_model_gen;\
endif
How can i replace the above logic, which include ch0-ch5 in one or two line. Similar to below one but it’s not working from system verilog point of view
`define csr_pkg(blk)\
`define CSR_``blk`` \
`ifdef CSR_ch*_ddr\
import csr pkg blk csr::*;\
csr_block_``blk`` reg model gen;\
else \
import csr pkg_blk csr::* \
csr_block_``blk``_csr reg_model_gen;\
endif