System Verilog checker

SystemVerilog
1

I want to write a system Verilog checker for this condition :
‘req’ signal should be high within 4 clock cycles of grant.

2

In reply to ankit96:

Property name;
@(posedge clk) req |-> ##[1:4] grant;
endproperty

3

In reply to Tunu:

thanks for the reply,
but I don’t want to write assertions , I want this method in checker .

4

In reply to ankit96:
Here is a checker for req and grant handshake, hope this helps.

  reg req;
  reg grant;
  reg clk;
  reg [2:0] count;
  reg req_asserted;
  always @(posedge req) begin
    req_asserted = 1;
    count = 4;
  end
  
  always @(posedge clk) begin
    if(req_asserted == 1) begin
      if(grant == 1 || req == 0) begin
         req_asserted = 0;
      end
      else begin
        count = count -1;
        if(count == 0) begin
           $error ("Grant was not asserted!"); 
           req_asserted = 0; 
        end  
      end 
    end  
    else begin
      count = 4;
    end   
  end
5

In reply to ankit96:

Realize that the word “checker” means different things to people writing in SystemVerilog and can be implemented with many different constructs. In fact “checker” is a keyword SystemVerilog for construct encpsulating assertions with other behaviors.