Question is
Signal A is a pulse , unless signal B is asserted.
how can we write an assertion for this ??
In reply to kushagar:
Weak requirements.
Try solving it with straight code first
task automatic t_AB;
if (B) A==??;
else begin
A== ? ;
@(posedge clk)
A= !?; //??
endtask
always @(posedge clk)
fork t_AB();
join_none
See my paper 1) SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy
After you express your assertion with the SystemVerilog task approach, translate it into SVA, or just present your solution, and we can help you. The way you expressed your requirements are too vague.
FOLKS! Many of you want an assertion with very very weak and ambiguous requirements.
If you clarify the requirements, the assertions are much easier to write.
Also, complex assertions can be broken into multiple smaller ones.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
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- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
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