System Verilog assertions

SystemVerilog
,
1

Hi

sequence s;
  int st = st1+14;
  $rose(s1) ##1 (~s2 && st>0, st--)[*] 
endsequence

property p_block;
  @(posedge clk) disable iff (!rst)

     s  |-> ##1  $fell(s3);
endproperty


As soon as s1 goes high this not repeating and st doesn't decrement (~s2 && st>0, st--)[*] 

Am i missing something
2

In reply to ben@SystemVerilog.us:

A clarification:
A ##1 b[0] is
A ##1 empty which is just A according to the Lrm

My model was based on a simulation

3

In reply to ben@SystemVerilog.us:

Hi Ben,

I got Error when i use :

$rose(s1) ##1 (~s2 && st>0, st-=)[*1:$]

Illegal declaration for -=
4

In reply to tejasakulu:

This simple example compiles and elaborates ok

 
// Code your testbench here
// or browse Examples
// Code your testbench here
// or browse Examples
module m;
  bit clk, a, b;
  property pn;
    int v=10;
    (a, v-=1)[*2] |-> v==0;
  endproperty 
  A1: assert property(
    @(posedge clk) pn); endmodule