→ Because of the delay 100ps, The fell and rose is sampled on the next clock edge.So assertion is failing for 10 clock cycles.if i put11 clock cycles the assertion works/Passing.
My question is ::: 1) how to handle the delay of 100ps and check for the rose/fell of the reset_signal check ?
2) Is there any way to handle it in assertion?
3) Should be in designers point of view…?
Are you saying that relative to your TXCLK, reset_signal has a 100ps hold time, and of course TXCLK has a period > 100ps?
From your diagram above, ($fell(reset_signal)at the posedge of tick 2.
Then $rose(reset_signal)) should occur on the posedge of tick 12.
So this ($fell(reset_signal) |-> ##10 $rose(reset_signal)) should have worked.
Am I missing something?
If the 100ps is asynchronous, then it’s a different story.
Are you saying that relative to your TXCLK, reset_signal has a 100ps hold time, and of course TXCLK has a period > 100ps?
txclk >>100ps
Reset signal is toggling for exactly 10clock cycles.But w.r.t to the edge of the clock there is a delay of 100ps. If I check the duration between rise and fall its exactly 10 clock cycles.
From your diagram above, ($fell(reset_signal)at the posedge of tick 2.
Then $rose(reset_signal)) should occur on the posedge of tick 12.
So this ($fell(reset_signal) |-> ##10 $rose(reset_signal)) should have worked.
I have put 10 clock cycles, so evaluation starts from 2 and until 11.The value at (11th posedge) is still 0.so assertion fails at 12.
Completion of 10 clock cycles is done at 11th clk, by the time reset signal value is still… this is what i observed.
Delay in the signal is 100ps. Instead of starting form clock 1.It starts at clock 2
And the same delay is applicable to the rising edge.
Am I missing something?
7)Still its not so clear i will change the way I explain and let you know.
If the 100ps is asynchronous, then it’s a different story.
8)Its not asynchronous.
9)Its synchronous to clock.
The 100ps is a hold time, and has no effect on the assertion.
What you have as an assertion is correct. Below is a simple model, with a hold time (though not needed) along with the simulation results. It works as expected.
module risefall;
bit clk, a=1'b1;
ap_rf: assert property(@(posedge clk) $fell(a) |-> ##2 $rose(a) );
initial forever #5 clk=!clk;
initial begin
@(posedge clk);
repeat(200) begin
@(posedge clk);
#1;
if (!randomize(a)) $error();
end
end
endmodule
