[System verilog ] Accessing an array with range varying along with upper and lower limits and the width of the array

Hi

Want to access the array with different width sizes along with different upper and lower limits .

The Sample code is as follows (Ignore the begin/end syntax )

foreach(fields[i]) begin
         if(fields[i].get_name().substr(0,7) != "reserved")    begin
          const int lsb_i= fields[i].get_lsb_pos() ;
          const int msb_i = fields[i].get_lsb_pos() + fields[i].get_n_bits()-1;
          int size_of = msb_i - lsb_i + 1;
          if((r_data[msb_i -:size_of] ) ==( m_data[msb_i -:size_of] ) ) 
    begin
         `uvm_info(get_type_name(),$sformatf("Matching data for Reg %s with fields[i] %s read data = %0h and mirror_data = %0h @ Addr=%0h", regs[i].get_name(),                           fields[i].get_name() ,r_data ,m_data, regs[i].get_address()), UVM_MEDIUM);
    end
           else
          `uvm_error(get_name(),$sformatf("MIsMatching data for Reg %s with fields[i] %s read data = %0h and mirror_data = %0h @ Addr=%0h", regs[i].get_name(),                         fields[i].get_name() ,r_data ,m_data, regs[i].get_address()));  
         end

The Problem is with the BLOCK code ,

The array doesnt suppoort the indices for range being variable .

I get an error as follows :

if((r_data[msb_i -:size_of] ) ==( m_data[msb_i -:size_of] ) ) 
                                   |
xmvlog: *E,NOTPAR (/vobs/asic/hawkowl/src/jor/src/jor_top_sec/tb/lib/env/er_jor_insec_reg_seq_lib.svh,220|35): Illegal operand for constant expression [4(IEEE)].
          if((r_data[msb_i -:size_of] ) ==( m_data[msb_i -:size_of] ) ) 
                                                                 |
xmvlog: *E,NOTPAR (/vobs/asic/hawkowl/src/jor/src/jor_top_sec/tb/lib/env/er_jor_insec_reg_seq_lib.svh,220|65): Illegal operand for constant expression [4(IEEE)].

So please help me solving this issue .

Thanks in advance

In reply to rajivdesh:

Verilog does not allow integral operands having widths dynamically sized; their widths must be constant expressions computed at compile time. A const variable cannot be used in a constant expression because its value gets computed at runtime. In this case, the variables get initialized in each iteration of the foreach loop.

You can either write a for-loop comparing each bit

if(fields[i].get_name().substr(0,7) != "reserved")    begin
          int lsb_i= fields[i].get_lsb_pos() ;
          int msb_p = fields[i].get_lsb_pos() + fields[i].get_n_bits();
          bit match = 1;
          for(int idx=lsb_i; idx < msb_p; idx++)
            if( r_data[idx] != m_data[idx] ) begin
                match = 0; break;
            end
          if (match)
            `uvm_info(get_type_name(),$sformatf("Matching data for Reg %s with fields[i] %s read data = %0h and mirror_data = %0h @ Addr=%0h", regs[i].get_name(),                           fields[i].get_name() ,r_data ,m_data, regs[i].get_address()), UVM_MEDIUM)
           else
             `uvm_error(get_name(),$sformatf("MIsMatching data for Reg %s with fields[i] %s read data = %0h and mirror_data = %0h @ Addr=%0h", regs[i].get_name(),                         fields[i].get_name() ,r_data ,m_data, regs[i].get_address()))
end

Or you can create a mask

if(fields[i].get_name().substr(0,7) != "reserved")    begin
          int lsb_i  = fields[i].get_lsb_pos() ;
          int size_i = fields[i].get_n_bits();
          bit [$bits(r_data)-1:0] mask = 3(2'b1 << size_i) -1) << lab_i;
          if (r_data && mask == m_data && mask)
            `uvm_info(get_type_name(),$sformatf("Matching data for Reg %s with fields[i] %s read data = %0h and mirror_data = %0h @ Addr=%0h", regs[i].get_name(),                           fields[i].get_name() ,r_data ,m_data, regs[i].get_address()), UVM_MEDIUM)
           else
             `uvm_error(get_name(),$sformatf("MIsMatching data for Reg %s with fields[i] %s read data = %0h and mirror_data = %0h @ Addr=%0h", regs[i].get_name(),                         fields[i].get_name() ,r_data ,m_data, regs[i].get_address()))
end

All untested :)