System verilog

SystemVerilog
1

im writing a code to generate prime numbers but unable to compile . can you please help me how can call this function inside constraint checki_prime and make the condition true.


module test();
 
  class prime_num;
    
    rand logic [7:0] num_5;
   rand bit is_prime;
    constraint pr{is_prime == 1;}
    constraint prime_number{checki_prime(num_5) == 1;}
    
    bit function checki_prime(int num);
     if(num == 2 || num == 3) begin return 1;
       $display("prime number %d", num);
      
     end
     else if(num < 2 || num%2 == 0) begin return 0; begin
       $display(" not a prime number %d", num);
      
     end
      for(int i=3; i<=$sqrt(num)+1 ; i=i+2) begin
        if(num%i !=0 )   return 1;    $display("  prime number %d", num);

      end
      //$display("prime number %d", num);

    endfunction
  endclass
 
  prime_num num_2;
 
   initial
    begin
      num_2 = new();
      repeat(20)
        begin
          if(!num_2.randomize())
            begin
              $display("Randmoization failed");
              $finish;
            end
          $display("number generated is %0d", num_2.num);
        end
    end

                   endmodule

Errors getting in EDA playground

MESSAGE “Pass 1. Scanning modules hierarchy.”
ERROR VCP2020 “begin…end pair(s) mismatch detected. 1 tokens are missing.” “testbench.sv” 28 11
ERROR VCP2020 “module/macromodule…endmodule pair(s) mismatch detected. 1 tokens are missing.” “testbench.sv” 28 11
ERROR VCP2000 “Syntax error. Unexpected token: endclass[_ENDCLASS]. This is a SystemVerilog keyword since IEEE Std 1800-2005 and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for compilation.” “testbench.sv” 28 11
ERROR VCP2020 “module/macromodule…endmodule pair(s) mismatch detected. 1 <module/macromodule> tokens are missing.” “testbench.sv” 46 29
ERROR VCP2000 “Syntax error. Unexpected token: endmodule[_ENDMODULE].” “testbench.sv” 46 29
FAILURE “Compile failure 5 Errors 0 Warnings Analysis time: 0[s].”

2

In reply to srikanth.verification:

sorry calling in intial block num_2.num_5 but getting this error. ERROR VCP2020 “begin…end pair(s) mismatch detected. 1 tokens are missing.” “testbench.sv” 28 11
ERROR VCP2020 “module/macromodule…endmodule pair(s) mismatch detected. 1 tokens are missing.” “testbench.sv” 28 11
ERROR VCP2000 “Syntax error. Unexpected token: endclass[_ENDCLASS]. This is a SystemVerilog keyword since IEEE Std 1800-2005 and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for compilation.” “testbench.sv” 28 11
ERROR VCP2020 “module/macromodule…endmodule pair(s) mismatch detected. 1 <module/macromodule> tokens are missing.” “testbench.sv” 46 29
ERROR VCP2000 “Syntax error. Unexpected token: endmodule[_ENDMODULE].” “testbench.sv” 46 29
FAILURE “Compile failure 5 Errors 0 Warnings Analysis time: 0[s].”

3

In reply to srikanth.verification:

Please use code tags. I have added them for you.

Your function declaration is incorrect. You should have:


function bit checki_prime(int num);

Your error message also states “begin…end pairs(s) mismatch detected”. This is because your begin/end statements don’t match.