What is system bus interface protocol?
How to implement system bus interface in verilog?
How to create/declare a packet(with header as sop and CRC as eop) in verilog?
If I want to transfer data packet wise from master interface to slave interface then how to create packet at master side and how to check CRC at slave side after reception of data packet?
In reply to Mittal Maru:
If I want to transfer data packet wise from master interface to slave interface then how to create packet at the master side and how to check CRC at the slave side after reception of data packet?
There are several standard protocols for transferring data across devices, such as AMBA, UART.
They all involve a bus acquisition (if multiple devices), a clock and start of message synchronization mechanism between the transmitter and receiver; a data transfer block, a check (such as CRC).
Am giving you a copy of my book Component Design by Example
http://systemverilog.us/vf/cmpts_by_example.pdf
http://systemverilog.us/vf/CMPTS_VHDL.zip
This book explains the UART model as a vehicle to demonstrate the design processes from requirements to verification. You could easily modify to model to packets larger than 8 bits. Though that may solve your problem, the best answer is to look at your requirements and see if you can adopt a standard bus interface. In any case, the UART model may help you understand the issues.
NOTES ABOUT THE BOOK AND CODE
This book was written in 2001. Since then technology has changed, and the verification methodologies have improved. Specifically, Verilog matured to become SystemVerilog and assertion languages matured along with formal verification. I need to caution the readers of this book that the verification methodologies offered here are outdated and are not recommended. The guidelines in writng specifications and requirements still hold.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
What is datalink interface protocol?
How to use it as slave interface?
In reply to Mittal Maru:
What is datalink interface protocol?
How to use it as slave interface?
From your question, it seems that you have very little experience in the fundamentals of digital designs. This knowledge can be acquired in a variety of ways:
- School, not sure if they actually go to real designs
- Training centers, In India My co-authors run http://www.cvcblr.com/
- On the job training, typically through a project
- Tecnical books, In 2002 I captured in Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712 many digital design fundamentals starting from the types of registers, progressing to types of counters, then memories, async clocks and meta-stability, fifos (synchronous & asynchronous), verification, control machines (cpu with fsm & microcode, & arithmetic machines.
With an understanding of digital fundamentals and an understanding of the requirements, one can construct the architecture and then the implementation.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment