Synthesizable loop

SystemVerilog
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1

Hello guys

Need a clarification on synthesizable loop construct.

I know for loop is not synthesizable.
Is that foreach synthesizable??

If not what is the alternative for the below piece of code in SystemVerilog to be synthesizable.

foreach (holder[item]) begin
     holder[item] = 0;
end

Please do suggest me to know more about synthesizable constructs to be more efficient on my designs.

Thanks and Regards
Manjush

2

In reply to manjush_pv:

A for loop is synthesizable as long as the compiler can determine the number of loop iterations statically. Then it will unroll the loop.

A foreach loop is even easier to synthesize because as long as the array is a fixed size, the loop iteration count is fixed as well.