Synthesis of dynamic array datatype is not supported; signal 'info_qid_q' will be ignored

SystemVerilog
, ,
1

Hi,

For assertion based verification, when I try to add aux code that uses queue, I get this compilation error while using vcs jaspergold tool:

Error : synthesis of dynamic array datatype is not supported; signal ‘info_qid_q’ will be ignored
signal ‘info_qid_q’ will be ignored

Are queues not allowed in aux code? If so, what other way can I use to get behavior similar to queues?



int info_qid_q[$:1024];
//also tried : int info_qid_q[$];


always @(posedge i_clk or  negedge i_rst_n)
    begin
      if(!i_rst_n)
      begin
       info_qid_q = {}; //clear the q 
      end
      else if(cmf_req)
       info_qid_q.push_front(info_qid); //store
    end

Thank you.

2

In reply to UVM_learner6:

A bounded queue should be synthesizable, but you have run into a tool specific issue. This Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues.

Working around the problem means you need to use a fixed sized array and create a pair of read/write index registers to select the element that gets accessed every time you would have done a push or pop.