Syntax error :token is '['

SystemVerilog
1

hi
i am trying to compile this code:

module MAC #() (
	clk, rst, a, b, prev_f, f
);

	parameter ELEM_IN_SIZE = 8;
	parameter ELEM_OUT_SIZE = 16; //ELEM_IN_SIZE*2
	
	input clk, rst;
	input signed [ELEM_IN_SIZE-1:0] a, b;
	input signed [ELEM_OUT_SIZE-1:0] prev_f;
	output signed [ELEM_OUT_SIZE-1:0] f;
	logic [ELEM_IN_SIZE-1:0] l1,l2;
	logic [ELEM_OUT_SIZE-1:0] mul,add,f1;
	always_ff @(posedge clk or posedge rst) begin
		if(rst) begin
			l1 <= 0;
			l2 <= 0;
			f1 <= 0;
		end
		else begin
			l1 <= a;
			l2 <= b;
			f1 <= prev_f;
		end
	end
	always_ff @(posedge clk or posedge rst) begin
		if (rst) begin
			f <=0;
		end
		else begin
			f<=add;
		end
	end
	always_comb  begin
			mul = l1 * l2;
			add  = mul + f1;
	end	
	
endmodule : MAC

and every time i try to i get this error:
Error-[SE] Syntax error
Following verilog source has syntax error :
“MAC.sv”, 20: token is ‘[’
logic [ELEM_IN_SIZE-1:0] l1,l2;

can you help?
thanks

2

In reply to sharino:

Your code works for me, except you need to add another declaration for ‘f’ since it is declared as a net only.

You should contact your vendor support team for additional assistance.

3

In reply to sharino:

Output ‘f’ can’t be driven from an always_ff block like that, since it’s declared as a net. You’ll need


output logic signed [ELEM_OUT_SIZE-1:0] f;

Furthermore, since you are harnessing the power of SystemVerilog you can do away with K&R port declarations, and give types to the parameters:


module MAC #(parameter int ELEM_IN_SIZE = 8, parameter int ELEM_OUT_SIZE = ELEM_IN_SIZE * 2)
(
    input logic clk,
    input logic rst,
    input logic signed [ELEM_IN_SIZE - 1:0] a, b,
    input logic signed [ELEM_OUT_SIZE - 1:0] prev_f,
    output logic signed [ELEM_OUT_SIZE - 1:0] f
);
4

In reply to sbellock:

thank you both
can you explain a little what is a K&R port? what is the idea behind it? can’t find any explanation online

5

In reply to sharino:

You need time machine to go back to the late 1980’s.

These are also known as ANSI-C style ports, added by Verilog-2001. See section 23.2.1 Module header definition in the IEEE 1800 LRM. Their main advantage is having to mention a port name in a declaration only once, instead of up to three times (for order, direction, and type).