Syntax error on compilation

SystemVerilog
1

Every time , I compile any code, it gives me an error “module” syntax error

link of the photo is below, kindly use it as reference

https://drive.google.com/file/d/1oCuV2tcyifMr0T3Q2jWzrv8pJwUOEVRn/view?usp=sharing

2

In reply to ANMOL GUPTA:

It would really help to see the actual code as text, not as a picture. See this article on posting code.

Usually syntax errors like this are because of a problem before the module keyword.

3

In reply to dave_59:

here is the code

module mux_2x1_beh(m_out, A,B, select);
output m_out;
input A,B,select;
reg m_out;

always@(A or B or select)
if(select == 1)
m_out = A;

else 
m_out = B;
endmodule
4

In reply to ANMOL GUPTA:

The code you just posted compiles fine. Like I said, you need to look at anything that preceded this code in your compilation.

5

In reply to dave_59:

but sir , can’t figure out anything that leads to this error because it is coming on compilation of every code though code is running fine in EDA playgrounds

6

In reply to ANMOL GUPTA:

If you are compiling a list of files, try removing the file producing the error and see what happens.