In reply to Malai_21:
An until property can be of many forms: strong or weak, and of overlapping or non-overlapping :
Weak non-overlapping form property_expr1 until property_expr2
Strong non-overlapping form property_expr1 s_until property_expr2
weak overlapping form property_expr1 until_with property_expr2
strong overlapping form property_expr1 s_until_with property_expr2
Rule:  An until property of the non-overlapping form (i.e., until, s_until) evaluates to true if property_expr1 evaluates to true at every clock tick beginning with the starting clock tick of the evaluation attempt and continuing until at least one tick before a clock tick where property_expr2 (called the terminating property) evaluates to true.
// if CS goes low, the "hold" and "wp" has to be 1 until CS goes high.
// it was not giving any error but the assertion was not finished.
// it was active even CS goes high.
$fell(cs_n_out) |-> (hold_n_out == 1 && wp_n_out == 1) until ($rose(cs_n_out));
!cs_n_out |-> (hold_n_out == 1 && wp_n_out == 1)[*1:$] ##1 ($rose(cs_n_out));
For training, consulting, services: contact http://cvcblr.com/home
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
1) SVA Package: Dynamic and range delays and repeats https://rb.gy/a89jlh
2) Free books: Component Design by Example https://rb.gy/9tcbhl
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
- SVA Alternative for Complex Assertions
- SVA in a UVM Class-based Environment
- Understanding the SVA Engine,