In reply to Pavan Kumar Kollipara:
This is because valid gets sampled at the beginning of the time-step before the clock or reset edges. Also, your assertion only works if reset is held low over a the posedge of clock. You might want to write this as
property VALID_LOW_IN_RESET;
@(posedge clk) \
!reset_n |-> valid == 0
endproperty: VALID_LOW_IN_RESET
VALID_LOW_IN_RESET: assert property (VALID_LOW_IN_RESET)
else $error("%0t:%m. VALID IS HIGH IN RESET STATE.", $time);You might want to look at section 16.12.14 Abort properties in the IEEE 1800-2017 SystemVerilog LRM
