SVA valid low in reset state

SystemVerilog
, ,
1

Hello,

My assertion is failing only when reset going low and valid is going low in that point only my assertion is getting failed. In all the cases it is passing except that reset transition state from high to low.


property VALID_LOW_IN_RESET;
      @(posedge clk) disable iff (reset_n == 1) 
         (valid == 0);
   endproperty: VALID_LOW_IN_RESET

   VALID_LOW_IN_RESET: assert property (VALID_LOW_IN_RESET)
               else $error("%0t:%m. VALID IS HIGH IN RESET STATE.", $time);

Thanks,
Pavan

2

In reply to Pavan Kumar Kollipara:

I couldn’t fully get your question or issue with this SVA but here is what it is trying to do

1)we are asserting the property at every rising edge of the clock
a)If reset_n is HIGH then we disable the assertion, we are not checking anything at this
clock edge
b)If reset_n is LOW then you are asserting that valid signal must be LOW at this clock
edge

3

Hello Hsam,

Thanks for your reply,

My Assertion is fine but in all cases. But, in one case and in one point where reset and valid both are going down at a time at posedge of clock. then my assertion is getting failed. I am not knowing why it is getting failed only at that time.

4

In reply to Pavan Kumar Kollipara:

This is because
valid gets sampled at the beginning of the time-step before the clock or reset edges. Also, your assertion only works if reset is held low over a the posedge of clock. You might want to write this as

property VALID_LOW_IN_RESET;
      @(posedge clk) \
         !reset_n |-> valid == 0
   endproperty: VALID_LOW_IN_RESET
 
   VALID_LOW_IN_RESET: assert property (VALID_LOW_IN_RESET)
               else $error("%0t:%m. VALID IS HIGH IN RESET STATE.", $time);

You might want to look at section 16.12.14 Abort properties in the IEEE 1800-2017 SystemVerilog LRM

5

Thanks Dave,

This is working fine.