SVA: procedural assertion in a loop

English is not my mother tongue, hope I will be understood.
I want to write a checker for a block that receives a vector at the input, where each member of the vector represents a specific place in the design that turned that member on or off. Each such organ also comes with a certain clock, which is not necessarily the same as the block’s clock, therefore every such input goes through an internal block that synchronizes it to the system’s clock.
Each such entry also has a mask and an enable which are also entered as a vector. The system is only interested in them after synchronization.
To verify each entry I put the Assertions into a GENVAR loop with a reference to the loop variable. It turns out that this is a violation of the language rules.
Is there a way that I can write a general ASSERTION, and insert into it each time a certain member of the input vector?
I thought of using define, and calling it according to the number of entries, but I would love to hear if there are other ways.
This is the error message I get when I try to run with the loop variable:
Procedural assertion ( i.e., assert, assume or cover property) is not allowed in looping statement. Only immediate assertions are allowed in this context.
Thank you

In reply to OE93:
SHow us your genver loop and some code, including the data structure.
Since everything is synchronized to a clock, use that clock for the assertions.

In reply to OE93:

The error messages does not match your descriptions. There are generate-for loops and procedural-for loop. Your description mentions the generate-for loop, but not the procedural-for loop. Showing some code that represents your situation will help a lot.