SVA or Not SVA? My creation at a delicious healthy vegetarian omelet

SystemVerilog
1

I posted the following on LinkedIn and got some interesting responses:
My creation at a delicious healthy vegetarian omelet

[Vikas] Did you verify with sva it met the specs
[Ben]


ap_omelet: assert property(@(posedge minute_clk)
   ingredients== {mushrooms, onions, oil, broccoli, bell_pepper} |->
            ##[3:5] spinach ##2 cheddar #-# cook until ready);
// Note the followed-by operator linking a sequence to a property

[Ben] This video shows that SVA can be used to describe procedures or a set of requirements to describe/test a subsystem that has sequential steps.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  2. Free books: Component Design by Example https://rb.gy/9tcbhl
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers:

Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/