SVA global variable

SystemVerilog
1

Hi,

I want to add a check in the test that all assertion have been tested,
So I added a flag to every property,
How do I pass the flags to test?
(the flags are local variables)

example:
assertion to expected that rst_archiplage == 0 after rose mbist_done

property reset_before_mbist_p;
logic reset_before_mbist_act;
@(posedge in_clk)
disable iff (rst_pwr_ctrl === 1)
(1, reset_before_mbist_act = 1 && $rose(mbist_done)) |-> rst_archipelago == 0;
endproperty

reset_before_mbist_a: assert property (reset_before_mbist_p) else `uvm_error(“everest_assertions”, $sformatf(“mbist_en rised before released reset.”));
// -------------------------------------

reset_before_mbist_act - is flag when assert done,

thanks

2

In reply to saraTel:

  1. The code used to check if an assertion is exercised incorrect because that variable is set to 1 at every clocking event, even if the antecedent is a no match.
 


(1, reset_before_mbist_act = 1 && $rose(mbist_done)) |->
... // not this 

$rose(mbist_done) ##0 (1, reset_before_mbist_act = 1)|->... //variable set only is antecedent is a match

On “How do I pass the flags to test?”, are you talking about initiating a new test based on the results? Tools provide coverage information.
Ben systemverilog.us

3

In reply to ben@SystemVerilog.us:

thank you about your answer…
Can you show me an example of how I collect coverage for the above assertion?
I want to collect coverage to reset_before_mbist_act variable.
Where do I write the code, and where do I see the results?

thank in advance.

4

In reply to saraTel:
Below is a link from my SVA Handbook 4th Edition that addresses this topic. It was written by my co-author. Those pages fom the book should provide you with a direction, but you’ll need to do more digging and experiments to get what you need. !800 has also more definitions on the APIs.
http://systemverilog.us/vf/coverage_api.pdf

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

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5

In reply to ben@SystemVerilog.us:

How can I pass this variable to the test?
This is defined as a local variable

6

In reply to saraTel:

One possibility is to use files where one test writes its results that can then be read by another test.
Perhaps there are other methods.
Ben systemverilog.us

7

In reply to saraTel:

Hi,
I want to add a check in the test that all assertion have been tested,

BTW, most simulation tools automatically provide this as coverage information.

8

In reply to dave_59:

I believe that what SaraTel was attempting to do is to automatically tune follow up tests based on previous tests, thus the need to transfer information across tests.
Ben systemverilog.us