SVA first_match usage

SystemVerilog
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1

Hi,

I’m trying this sequence in my property and got an error saying “Property operator usage is not allowed in sequence context. LTL Property operator is used in sequence context.”

I have used it in the same way in other properties and it compiles without any issues. Not sure why it’s a problem now. Please help.

@(posedge clk) sig1 == 4'h5 |-> strong(first_match(##[0:$] $fell(sig2))) ##[0:$] ($rose(sig3) && sig4);

Thanks

2

In reply to nimitz_class:

Like the message correctly says, strong is a property operator and you are using it in the beginning of a sequence.

strong(...) ##[0:$] ($rose(sig3) && sig4);