(SVA) Concurrent Assertions on the same signal

SystemVerilog
1

Hi All,

If I assert a signal to some value (concurrent assertion), could I then change this assertion to another value (also concurrent assertion)?

How? Will the second assertion automatically disable the first one once it was done on the same signal but with a different value?

Thank you!

2

In reply to dmitryl:

This sounds like a rhetorical question; what are your requirements?
Ben