SVA: check an event occurred in a window of time in the past

SystemVerilog
,
1

Hi,

how can I write an SVA assertion checks the following behavior:
If B occurred, A must occurred within [1:20] cycles, this it can be easily checked via:


p1: assert property(
  @(posedge clk)
  B |-> ##[1:20] A;)

I want to check the other direction, if A occured
how can I check that it was due to B event, I thought to use $past() but it gives the previous value in a specific previously cycle how can predict a previous value within a window of time?


p2: assert property(
  @(posedge clk)
  A |-> B occurred in the past [1:20] window)

Thanks in advance.

2

In reply to Mohamed_TN:

p1 is the better way, but, if you must


p1: assert property(@(posedge clk)
    b |-> ##[1:20] a); // better 
    
    generate for (genvar i=1; i<=20; i++) 
        p1: assert property(@(posedge clk)
        a |-> $past(b, i)); 
    endgenerate

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

See Paper: 1) VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf

3

In reply to ben@SystemVerilog.us:

In this way the assertion will check B in each cycle in the window, consider the case when A is triggered by only one B event during the window [1:20].

4

In reply to Mohamed_TN:

In reply to ben@SystemVerilog.us:
In this way the assertion will check B in each cycle in the window, consider the case when A is triggered by only one B event during the window [1:20].


Again, this assertion is far better, and is more expressive
p1: assert property(@(posedge clk)
    b |-> ##[1:20] a); // better 

With the generate, you end up with 20 separate assertions, one or more of which may succeed if b was true at 1 or more previous cycles, and the others will fail. 
There is no $past with a range. 
The $past function provides the sampled value that an expression held in a previous nth cycle. The syntax of the function is: [1]
$past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])

    generate for (genvar i=1; i<=20; i++) 
        p1: assert property(@(posedge clk)
        a |-> $past(b, i)); 
    endgenerate
 The nature of the beast!

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

See Paper: 1) VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy
2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf

5

In reply to ben@SystemVerilog.us:

I don’t understand what do you mean by better and more expressive, the p1 checks one direction and it’s OK, my issue with p2 which check the other direction, I want to be sure that A must be triggered only by B, I can’t use the same approach of p1 since I need to go back in time and check if A occurred there was B occurred before it within the window of time [1:20],

I understand your solution based on loop generate, it needs a special filter to bypass the wrong failed assertions, it’s not easy I think.

Thanks for your answers,

6

In reply to Mohamed_TN:
OK, you can do this, that should work


    bit[1:20] pasts; 
    always  @(posedge clk) begin
      pasts <= {b, pasts[1:19]}; // shift right 
    end

    p1_past20: assert property(@(posedge clk)
     a |-> $countones(pasts) >= 1); 
    //b |-> ##[1:20] a);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

See Paper: 1) VF Horizons:PAPER: SVA Alternative for Complex Assertions | Verification Academy
2) http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf

7

Would this work?

sequence b_happened;
!a ##1 b ##[1:20] a;

endsequence

property p;
@(posedge clk)
$rose(a) |-> ##1 b_happened.triggered();
endproperty

8

In reply to ledzep_1988:


sequence b_happened;
  ##[1:20] b; // an end point at ##1 b==1, ##2 b==1, .. ##20 b=1
endsequence

A |-> B occurred in the past [1:20] window)
property p_BAD_STYLE;
 @(posedge clk)
  $rose(a) |-> ##1 b_happened.triggered;
endproperty[/quote]

// I rarely use the end points; it's an awkward way to look at things. 
// Better 
B |-> ##[1:20] A)