[SVA] Calling to assertions from within a task (and other stuff)

Hi All,

Is it possible to involve/set assertions from within a task?

Actually, I need to assert about 50 signals, which should have the same behavior.

So, I wrote a property, which receives a signal name as an argument and which will be used for the signals assertions.

Instead of writing 50 assertions in the TestBench, I’d like to include them in some task and call it only once from my TestBench. Is it possible? Howsome I’m receiving an error message that concurrent assertions cannot be included in the tasks.

So, what’s the solution? How to “pack” 50 assertions and call them from the TestBench only once?

Is it possible to create an alias for the assertion (or some another short way to call it)?

Can I use the $assertionon(<assertion_name>) and $assertionoff(<assertion_name>) to switch an assertion on/off? Is this useful? don’t slow the simulation?

Thank you!

In reply to dmitryl:


event go;
initial begin 
  @go 
  A1:assert property...  
  A2: assert property... 
end

task p(); // can be an always or initial 
 ... 
-> go;  // fires all assertions in the initial 
endtask  

Ben systemverilog.us

In reply to ben@SystemVerilog.us:

and how can I disable the assertion sinse they should be active just a certain time during the simulation?

What about the system tasks $assertionon() and $assertionoff()? Are they less useful? why?

Is it possible to “dis-assert” an assertion?

In reply to dmitryl:

…the assertion since they should be active just a certain time during the simulation

Assertions are statically allocated at elaboration time, just like module static variables are also statically allocated. Thus, at simulation time zero, all assertions exist but are not active. An assertion is active at its leading clocking event in the attempt phase if that attempt is successful. The assertion controls (e.g., $asserton, $assertoff) can be used to disable all, or selected assertions. From my SVA Handbook 4th Edition
$assertoff, $assertcontrol(OFF) This stops the checking of all specified assertions until a subsequent $assertcontrol with a control_type of 3 (On). No new attempts will be started. Attempts that are already executing for the assertions, and their pass or fail statements, are not affected. Any queued or pending assertions are not flushed and may still mature. No new instances of assertions are queued. The assertions are re-enabled with a subsequent $assertcontrol with a control_type of 3 (On).
This control_type value does not affect expect statements. For example,
**$assertcontrol(**OFF); // using default values of all other arguments

Tus,

and how can I disable the assertion since they should be active just a certain time during the simulation? What about the system tasks $assertionon() and $assertionoff()? Are they less useful?

Yes, you can use the assertion controls to enable or disable the assertions. If disabled, no new ones will be active.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr


See Paper: VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy

In reply to ben@SystemVerilog.us:

  1. all initial block will start executing at zero simulation time right, then if you are firing all the assertions in the initial block then it will check only once right. assertions on every signal should check for the entire simulation. to do that what we need to do?

In reply to vickyvinay:

Write the concurrent assertions outside the initial.
A1:assert property…
A2: assert property…