[SVA] Bus values weighted randomization

[ldm_as]

Hi All,

I have a 8-lines bus. I’d like to randomize it in the following way:

• 80% of time the bus should have 8’hFF value
• each line of the bus should have a value 0 for 20% of time and value 1 for 80% of time

How could I constrain this randomization without UVM?

Thank you!

[ben2]

In reply to ldm_as:
/ I have a 8-lines bus. I’d like to randomize it in the following way:

• 80% of time the bus should have 8’hFF value
• each line of the bus should have a value 0 for 20% of time and value 1 for 80% of time /
  // Unclear requirements. Assuming:
  // I have 8 lines, each 8-bit wide
  // 80% of the time, each of the line has a value of 8’hFF
  // 20% of the time, each of the lines has a value of 0 or 1

import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    bit clk, active; 
    byte line[0:7]; //  8 lines 
    byte data; // data hen active
    initial begin : init
        repeat(200) begin : r200
            @(posedge clk);   
            if (!randomize(active, data)  with 
            { active dist {1'b1:=80, 1'b0:=20};
              data dist {1'b1:=1, 1'b0:=1};
             }) `uvm_error("MYERR", "This is a randomize error")
           if(active) for (int i=0;i<=7;i++) line[i]<=8'hFF; 
           else for (int i=0;i <=7;i++) line[i]<= data[i]; 
        end : r200 
    end : init
endmodule   

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

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• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
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[dave_59]

In reply to ldm_as:

You might want to look at distributed weightage constraint | Verification Academy