[SV LRM 2017] typed constructor call error

SystemVerilog
,
1

I try to make one example here for typed constructor . commented part runs well but this code is giving fatal error :

** Fatal: Illegal assignment to class work.testbench_sv_unit::packet #(int) from class work.testbench_sv_unit::packet #(byte)

1.) what can be possible reason for this?
2.)As per 8.12 Assignment, renaming, and copying of SV LRM 2017,

It shall be illegal to use a typed constructor call for a shallow copy

can someone elaborate this with small example?

2

When making a call to the constructor the class is parameterized with byte but for handle p2 data type is int. As both are of different data types you are getting an error.Do the changes as shown below.


class packet #(type T=int);
  T b;
  int a=5;
endclass



module abc;
  packet#(byte) p2, p1;
  
  initial begin
    p2 = packet#(byte)::new() ;
    //while doing shallow copy not to use typed constructor as in below line
    //p1 = packet#(byte)::new p2;  error not possible as per LRM
    p1 = new p2;// correct way to copy
  end
endmodule

Regards,
Shanthi
www.maven-silicon.com