[SV LRM 2017] Special provision of unpacked union

SystemVerilog
,
1

can someone help me understand this part of text extracted from SV LRM 2017,Section 7.3 unions:

"One special provision exists in order to simplify the use of unpacked unions: if an unpacked union contains several unpacked structures that share a common initial sequence and if the unpacked union object currently contains one of these structures, it is permitted to inspect the common initial part of any of them anywhere that a declaration of the complete type of the union is visible. Two structures share a common initial sequence if corresponding members have equivalent types for a sequence of one or more initial members."

Is it mean that union can contain structures?

2

In reply to juhi_p:
A union may contain any datatype. SystemVerilog does not define the layout in memory for any type, so unpacked unions are not that useful except for maybe this provision. If you have the following two structs in a union

  typedef struct {
    int A;
    real B;
    bit [31:0] C;
    int D;
  } s1_t;
  typedef struct {
    int A;
    real B;
    bit [15:0] C1;
    bit [15:0] C2;
    int D;
  } s2_t;
  union {
    s1_t s1;
    s2_t s2;
  } U;

The LRM says you can write to U.s1.A and read it back from U.s2.A intact (same for element B). But there is no similar guarantee for any other members. A compiler might choose to align C1 and C2 to 32-bit word boundaries. so there’s no guarantee how s1.C overlaps s2.C1 and s2.C2, or whether s1.D overlaps s2.D. Only packed unions guarantee alignment over bits.

3

In reply to dave_59:

Hi Dave,

How does packed unions guarantee alignment over bits? while largest sized variable of union (packed/unpacked) allocates memory and other variable share same allocated space. So, how does packed and unpacked union differ from each other.

Thanks,
Azhar

4

In reply to azharuddin:

Every member of a packed union must have exactly the same number of logical bits, so there are no alignment issues. Even 2-state versus 4-state bits are aligned even though they take different amounts of allocated memory.

With an unpacked union, there’s no alignment rules, and there’s not event a requirement that the members share the same memory. Since there are no pointers in SystemVerilog, you would never know the difference. And even it you could through observation of the values, there’s no guarantee that some optimization could change it, or it might work differently in another simulation.