In reply to azharuddin:
Every member of a packed union must have exactly the same number of logical bits, so there are no alignment issues. Even 2-state versus 4-state bits are aligned even though they take different amounts of allocated memory.
With an unpacked union, there's no alignment rules, and there's not event a requirement that the members share the same memory. Since there are no pointers in SystemVerilog, you would never know the difference. And even it you could through observation of the values, there's no guarantee that some optimization could change it, or it might work differently in another simulation.