[SV LRM 2017] multidimensional array

[juhi_p]

bit [1:5] [1:6] v4 [1:7] [1:8];

how it will look like in memory storage ? can you draw diagram of same?

[ben2]

In reply to juhi_p:

Used a simulation tool to visualize the structure.

Ben SystemVerilog.us

[juhi_p]

In reply to ben@SystemVerilog.us:

Thanks ben.

[dave_59]

In reply to juhi_p:

Also see Difference between Packed and UnPacked Arrays | Verification Academy