[SV LRM 2017] const variable in class is possible to have multiple assignment within class constructor

SystemVerilog
1

find example here. As per LRM

Instance assignment can only be done once in the corresponding class constructor.

.but example is working fine. Is it because at 0 time we are doing multiple assignment?

2

In reply to juhi_p:

Yeah simulators aren’t the best at enforcing checks of illegal behavior. Only one of the Big Four simulators flags this as an error.