SV-interface

SystemVerilog
,
1

What is the use of instantiating an interface inside another interface??
At what situations this will be helpful?

2

In reply to Dileep:

What is the use of instantiating an interface inside another interface??
At what situations this will be helpful?

It’s really a matter of style, but the issue, of course, is hierarchy. I recall an Intel CPU design that had 3 separate interfaces as part of the chip. These interfaces included:

  1. Backside, high speed for cash and fast memory
  2. Frontside, lower speed for IO and low speed bulk memory
  3. Test, for debug.
    Thus, I could define 3 separate SV interfaces and include them in a main CPU interface.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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