SV: Illegal argument to port

SystemVerilog
,
1

Hello!

I have a syntax error that was not popping up before.


// I am calling a task in the always block of a module w/ a as input and b as o/p from the task.
logic [3:0] b;
logic [7:0] a;
always @ (a) begin
grp_task (a,b);
end
task grp_task;
input [7:0] i1;
output [3:0] o1;
begin
o1 = (i1==2)? 'd4: (i1==4) ? 'd2 : 'dx;
end
endtask

I am getting this error as: Argument to inout/output/ref port must be an expression that is valid on the
left-hand side of a procedural assignment.

Any help is very much appreciated.

Thanks

2

In reply to bharath_1800:
I could not reproduce your problem, but I had to add module/ top;/endmodule around your code. Please edit your post to show exactly what your code looks like.

There are many other problems with your code. Like why you did not use @(a or b), why did you not use a function instead of a task.