SV Generate

SystemVerilog
, , ,
1

Do system Verilog support delays inside. Suppose I am using genvar to generate multiple clocks like below

reg [7:0]clk;  
     genvar i;
        generate
          for (i=0; i < 7; i++) begin
              #1 clk[i]=~clk[i];
            end
        endgenerate

I am getting an error: near "#": syntax error, unexpected '#'.
how can we resolve it, whether can I use delays inside generate block ?

2

In reply to SUNODH:

The clock delay needs to be inside an always block.


bit [7:0] clk;

for (genvar i = 0; i < 7; i++) begin : clk_block
   always #1 clk[i] = ~clk[i];  
end

which in this specific example is (mostly) equivalent to just


bit [7:0] clk;

always #1 clk = ~clk;