SV Constraint to generate number such that circular shifted number does not match the number itself

SystemVerilog
,
1

I am trying to constraint a number such that it’s right circular-shifted (max shift of 7) value does not match the randomized value.
But it is not generating the correct values, I see it getting randomized to EE, which is incorrect since circular right shifted (by 4) EE results in EE.

What am I missing?


rand bit [7:0] num;
constraint c {
					
	num != (num<<7) | (num >>1);
	num != (num<<6) | (num >>2);
	num != (num<<5) | (num >>3);
	num != (num<<4) | (num >>4);
	num != (num<<3) | (num >>5);
	num != (num<<2) | (num >>6);
	num != (num<<1) | (num >>7);
	}
2

In reply to dvengg:
Your problem is relational operators like ‘!=’ have higher precedence than the bitwise or ‘|’ operator.

Write your constraint as

constraint c {
	num != ( num<<7 | num >>1 );
	num != ( num<<6 | num >>2 );
	num != ( num<<5 | num >>3 );
	num != ( num<<4 | num >>4 );
	num != ( num<<3 | num >>5 );
	num != ( num<<2 | num >>6 );
	num != ( num<<1 | num >>7 );
	}

Look at table 11-2 in the IEEE 1800-2017 SystemVerilog LRM.

3

In reply to dave_59:

In reply to dvengg:
Your problem is relational operators like ‘!=’ have higher precedence than the bitwise or ‘|’ operator.
Write your constraint as

constraint c {
num != ( num<<7 | num >>1 );
num != ( num<<6 | num >>2 );
num != ( num<<5 | num >>3 );
num != ( num<<4 | num >>4 );
num != ( num<<3 | num >>5 );
num != ( num<<2 | num >>6 );
num != ( num<<1 | num >>7 );
}

Look at table 11-2 in the IEEE 1800-2017 SystemVerilog LRM.

Dave,

Could you please elaborate on your solution?

4

In reply to imajeeth:

Look at the placement of parenthesis