Sv code to increase or decrease the clock frequency

SystemVerilog
1

Hi,

How to generate a clock having trim[3:0] bit in system verilog.
If my nominal trim[3:0] bit = 1000 for this trim bit, clock has to be in 26kHz frequency, as trim bit increases (i.e. 1000 - 1111) clock has to gradually increase by 10%, if trim bit decreases(i.e.1000 - 0000) clock frequency has to gradually decrease by 10%.

Kindly please help me in getting the logic.

Thanks in advance.

I have tried the following code:

`timescale 1ns/1ps
module clk_freq(en, clk,  trim, clk_out);
input [3:0] trim;
input logic en;
input logic clk;
output logic clk_out;

integer count =8;
real delay;


initial begin 
clk_out =0;
delay= 19230;
end 

always @(posedge clk)
begin 
if (trim == 4'b1000 && en ==1)
	begin 
	#delay clk_out = ~clk_out;
	end 

else if (trim >= 4'b1000 && en ==1 )	
	begin
	count <= count +1;
	
	for (count =8; count <= 15; count++)
	begin 
	delay = delay + (10/100);
	#delay clk_out = ~ clk_out;
	end 
end

else if (trim <= 1000 && en ==1 )
		begin 
		count <= count -1 ;
		
		for (count = 8; count >=0; count --)
		begin 
	delay = delay - (10/100);
	#delay clk_out = ~ clk_out;
	end 
end
end
endmodule

module tb_clk_freq();
logic clk, clk_out;
reg en;
reg [3:0]trim;

clk_freq A1(en, clk, trim, clk_out);

initial
 begin 
clk = 0;
en =0;
trim = 4'b0;
end 

always begin 
#100 clk =~clk;
en = 0;
#10 en =1;
end 

always begin 
#50 trim = 4'd0;
#50 trim = 4'd1;
#50 trim = 4'd2;
#50 trim = 4'd3;
#50 trim = 4'd4;
#50 trim = 4'd5;
#50 trim = 4'd6;
#50 trim = 4'd7;
#50 trim = 4'd8;
#50 trim = 4'd9;
#50 trim = 4'd10;
#50 trim = 4'd11;
#50 trim = 4'd12;
#50 trim = 4'd13;
#50 trim = 4'd14;
#50 trim = 4'd15;
end
 endmodule
2

[i]In reply to cgales:

hi cgales,

yes, I have tried to generate a clock using a variable delay and count, but how will I include my trim bit in the code wrt to the count.

Thanks

3

In reply to Sushma kanaka:

You need to show what you have written already, preferably a complete example on EDA Playground. After posting your code, some recommendations can be made.

4

In reply to cgales:
Hi cgales,
This is the following SV code and tb:

`timescale 1ns/1ps
module clk_freq(en, clk,  trim, clk_out);
input [3:0] trim;
input logic en;
input logic clk;
output logic clk_out;
integer count =8;
real delay;

initial begin 
clk_out =0;
delay= 19230;
end 

always @(posedge clk)
begin 
if (trim == 4'b1000 && en ==1)
	begin 
	#delay clk_out = ~clk_out;
	end 

else if (trim >= 4'b1000 && en ==1 )	
	begin
	count <= count +1;
	for (count =8; count <= 15; count++)
	begin 
	delay = delay + (10/100);
	#delay clk_out = ~ clk_out;
	end 
end

else if (trim <= 1000 && en ==1 )
		begin 
		count <= count -1 ;
		for (count = 8; count >=0; count --)
		begin 
	delay = delay - (10/100);
	#delay clk_out = ~ clk_out;
	end 
end
end
endmodule



module tb_clk_freq();
logic clk, clk_out;
reg en;
reg [3:0]trim;

clk_freq A1(en, clk, trim, clk_out);

initial
 begin 
clk = 0;
en =0;
trim = 4'b0;
end 

always begin 
#100 clk =~clk;
en = 0;
#10 en =1;
end 

always begin 
#50 trim = 4'd0;
#50 trim = 4'd1;
#50 trim = 4'd2;
#50 trim = 4'd3;
#50 trim = 4'd4;
#50 trim = 4'd5;
#50 trim = 4'd6;
#50 trim = 4'd7;
#50 trim = 4'd8;
#50 trim = 4'd9;
#50 trim = 4'd10;
#50 trim = 4'd11;
#50 trim = 4'd12;
#50 trim = 4'd13;
#50 trim = 4'd14;
#50 trim = 4'd15;
end
 endmodule
5

In reply to Sushma kanaka:

Please use code tags making your code easier to read. I have added them for you.

It is very difficult to read the code you have written as it is mostly non-functional.

10/100 is alway 0 (integer division)

en will be in a race with clk.

How are different trim values supposed to affect the clock period.

clk has a period of 200 ns (5Mhz), yet you change trim every 50ns.

Is this code supposed to be synthesizable or just for a testbench?

6

In reply to dave_59:

Hi Dave,

yes the code has to be synthesizable and not just for testbench.
here I have taken a reference frequency as 26Khz, for the default trim bit 1000, if my trim bit changes from 1000 t0 0111 the clock_out frequency has to decrease by 10% (now clock_out has to be in 23.4kHz (i.e. decrease in 10% of reference frequency)
if the trim bit changes from 1000 to 1001 then clock_out frequency has to increase by 10%.

Thanks